Re: Burning FET's and driver troubles
Posted: Fri Dec 10, 2010 7:16 pm
@Doug,
>the bottom one
Yes, that is precisely the shot that is bothering me (pulling the fets out of the on state). I am making all of these measurements with the ground clip of the scope lead connected to the negative line of the power supply
(marked '- Smoothed DC line' in the schematic), because this is a floating supply. Sorry about the focus - I have ordered an optical RS232 cable for that scope, I should have it next week. The blue trace in that bottom scope image is 10V/div.
Thanks for your perseverance with this.
Here is the propaganda from the SPW47N60C3 datasheet:
VDS @ Tjmax 650 V
RDS(on) 0.07 Ω
ID 47 A
* Worldwide best RDS(on) in TO247
* Ultra low gate charge
* Periodic avalanche rated
* Extreme dv/dt rated
* Ultra low effective capacitances
@Chris
The supply rail is fed by 230VAC -> 10Amp Variac -> 10Amp Rectifier -> 2X 4700uF 400VDC electrolytic capacitors in parallel. So that is a fairly direct and hefty supply, I would have thought? I can increase the cap bank to 10X 10000uF 450VDC with some nice 700amp bus bars if you think it would help? What is happening here really cuts to the heart of the problem that I have been experiencing with this project from day one. That is, the plasma shorts out the power supply; the high voltage drops from 40kV down to around 1kV. It's a dead short, effectively. That is why I chose a fairly high frequency (40KHz) when I was doing the voltage multiplier ladder calculations - to prevent the voltage from sagging (before I built the stack). But it seems to make no difference. I guess I need larger caps in the stack, to move more current through at this pressure. I have no idea what current the load is pulling, all attempts to measure it have been meaningless, and I am not keen on trying to measure it at the stack output like Farnsworth did. I measure the current draw on the variac, and have seen this go quite happily up to 10amps, which is scary. I know that this whole issue goes away at lower pressure, but it would be great to have a supply that could deliver, regardless of the pressure.
I have two 3-phase 500VDC 50amp power supplies standing by, with a 7kW 3-phase generator and 12 amplifier modules which weigh 50kg's each. With the CT transformer that is on route, that is over 800kg's, which I think is a nice way to measure power This arrangement will surely vaporize the grid and probably a fair portion of the tank as well. Doug is trying to assure me that finesse is the better option, but after 3 years my patience is wearing thin.
>a low-ish ESR cap of a uF or two up close to the FET
This is interesting - I have two .47uF low ESR bootstrap caps on the driver circuit, but they are nowhere near the fets. The driver is shielded and is around 6inches away from the H-bridge circuit. If I needed more capacitance near the fets wouldn't we see the gate waveform being pulled down? I have added some details to the schematic. I will post some pics of the entire setup tomorrow...
>the bottom one
Yes, that is precisely the shot that is bothering me (pulling the fets out of the on state). I am making all of these measurements with the ground clip of the scope lead connected to the negative line of the power supply
(marked '- Smoothed DC line' in the schematic), because this is a floating supply. Sorry about the focus - I have ordered an optical RS232 cable for that scope, I should have it next week. The blue trace in that bottom scope image is 10V/div.
Thanks for your perseverance with this.
Here is the propaganda from the SPW47N60C3 datasheet:
VDS @ Tjmax 650 V
RDS(on) 0.07 Ω
ID 47 A
* Worldwide best RDS(on) in TO247
* Ultra low gate charge
* Periodic avalanche rated
* Extreme dv/dt rated
* Ultra low effective capacitances
@Chris
The supply rail is fed by 230VAC -> 10Amp Variac -> 10Amp Rectifier -> 2X 4700uF 400VDC electrolytic capacitors in parallel. So that is a fairly direct and hefty supply, I would have thought? I can increase the cap bank to 10X 10000uF 450VDC with some nice 700amp bus bars if you think it would help? What is happening here really cuts to the heart of the problem that I have been experiencing with this project from day one. That is, the plasma shorts out the power supply; the high voltage drops from 40kV down to around 1kV. It's a dead short, effectively. That is why I chose a fairly high frequency (40KHz) when I was doing the voltage multiplier ladder calculations - to prevent the voltage from sagging (before I built the stack). But it seems to make no difference. I guess I need larger caps in the stack, to move more current through at this pressure. I have no idea what current the load is pulling, all attempts to measure it have been meaningless, and I am not keen on trying to measure it at the stack output like Farnsworth did. I measure the current draw on the variac, and have seen this go quite happily up to 10amps, which is scary. I know that this whole issue goes away at lower pressure, but it would be great to have a supply that could deliver, regardless of the pressure.
I have two 3-phase 500VDC 50amp power supplies standing by, with a 7kW 3-phase generator and 12 amplifier modules which weigh 50kg's each. With the CT transformer that is on route, that is over 800kg's, which I think is a nice way to measure power This arrangement will surely vaporize the grid and probably a fair portion of the tank as well. Doug is trying to assure me that finesse is the better option, but after 3 years my patience is wearing thin.
>a low-ish ESR cap of a uF or two up close to the FET
This is interesting - I have two .47uF low ESR bootstrap caps on the driver circuit, but they are nowhere near the fets. The driver is shielded and is around 6inches away from the H-bridge circuit. If I needed more capacitance near the fets wouldn't we see the gate waveform being pulled down? I have added some details to the schematic. I will post some pics of the entire setup tomorrow...