Re: Burning FET's and driver troubles
Posted: Sat Nov 20, 2010 12:25 pm
>You're going to need more drive, or less fet.
I have replaced the SPW47N60C3 fets with IXFH52N30P (52A, 300V). If/when they burn, I will get some IRFP450.
>those rises and falls are just too slow.
I have 6 ohm resistors at the gates and 470nF ultralow tantalums as bootstrap caps. When correctly tuned, this arrangement with the new fets seems to give a reasonable rise time. See pic 'LO2 & Output of same' (I measure the duration of the on pulse=13.8uS, rise time=1.6uS, fall time=0.8uS. So risetime is around 11% of on duration and 6% of total time. One complete cycle = 28uS = 35.7KHz)
The fets are staying cold at low or no load, but still at low voltage...
>if I could see one of the bridge outputs into the load.
See same pic as above - blue trace is gate, red trace is output of fet board at transformer primary.
>but you need bulk filtering.
I have connected two 4700uF @ 400VDC caps in parallel across the rails, so it's all smooth DC now, I'm also driving the chip with a large 12V battery.
I have added a snubber between the two output points (1000pf and 100ohms, 50w resistor) and it does not seem change much (tried different caps and resistor values). This is still with the main rail voltage at 10VDC, so perhaps when I turn things up it will make a difference?
>A key diagnostic is what does the output do during that dead time.
I identified the deadtime (see pic 'deadtime between the gates'), and then looked at this same time at the output. See pic 'Output during deadtime' - blue trace gate, red trace output. It looks to me like the output flies to the other polarity, pretty hard.
I have added a pic of the chip output without the fets connected, red trace is low gate signal, blue trace is high gate signal. What's with the little 'trough' before the rise on the high gate signal? And the little notch knocked out of the pulse just before the fall? I understand this is the deadtime, but do you know why it effects the high pulse like this, and not the low one? This little 'disturbance' is what is generating the more serious glitches and ringing in the fets... I have posted a pic of the ringing on the gates due this deadtime 'trough'.
I have tuned for the lowest no-load current: 310mA @ 10VDC which is around 42.37KHz (this is where the glitches disappear, just the same as in your video) but cannot get rid of this nasty ringing effect). I am going to connect it to the stack and see what happens at higher voltages...
I have replaced the SPW47N60C3 fets with IXFH52N30P (52A, 300V). If/when they burn, I will get some IRFP450.
>those rises and falls are just too slow.
I have 6 ohm resistors at the gates and 470nF ultralow tantalums as bootstrap caps. When correctly tuned, this arrangement with the new fets seems to give a reasonable rise time. See pic 'LO2 & Output of same' (I measure the duration of the on pulse=13.8uS, rise time=1.6uS, fall time=0.8uS. So risetime is around 11% of on duration and 6% of total time. One complete cycle = 28uS = 35.7KHz)
The fets are staying cold at low or no load, but still at low voltage...
>if I could see one of the bridge outputs into the load.
See same pic as above - blue trace is gate, red trace is output of fet board at transformer primary.
>but you need bulk filtering.
I have connected two 4700uF @ 400VDC caps in parallel across the rails, so it's all smooth DC now, I'm also driving the chip with a large 12V battery.
I have added a snubber between the two output points (1000pf and 100ohms, 50w resistor) and it does not seem change much (tried different caps and resistor values). This is still with the main rail voltage at 10VDC, so perhaps when I turn things up it will make a difference?
>A key diagnostic is what does the output do during that dead time.
I identified the deadtime (see pic 'deadtime between the gates'), and then looked at this same time at the output. See pic 'Output during deadtime' - blue trace gate, red trace output. It looks to me like the output flies to the other polarity, pretty hard.
I have added a pic of the chip output without the fets connected, red trace is low gate signal, blue trace is high gate signal. What's with the little 'trough' before the rise on the high gate signal? And the little notch knocked out of the pulse just before the fall? I understand this is the deadtime, but do you know why it effects the high pulse like this, and not the low one? This little 'disturbance' is what is generating the more serious glitches and ringing in the fets... I have posted a pic of the ringing on the gates due this deadtime 'trough'.
I have tuned for the lowest no-load current: 310mA @ 10VDC which is around 42.37KHz (this is where the glitches disappear, just the same as in your video) but cannot get rid of this nasty ringing effect). I am going to connect it to the stack and see what happens at higher voltages...