Burning FET's and driver troubles

Things at the limits.

Burning FET's and driver troubles

Postby JonathanH13 » Wed Nov 17, 2010 12:14 pm

Probably like many of us out there, I have been having troubles with my high voltage power supply. Doug suggested that I take this up on the forum, and perhaps we can work through it together. The problem is that the FET’s in my H-bridge circuit keep blowing.

I see at least two main issues – 1) Driving the FET’s properly and 2) matching the driver circuit to the transformer and tuning to optimum frequency.

I have attached an image of the circuit – the schematic describes all the component details. I am also concerned with possible inductive and capacitive parasitics due to poor circuit layout, and so have also attached a PCB layout.

Some points to consider:

The full bridge driver IC (IRS2453) is RF shielded from the H-bridge, and the voltages produced by the IC are around 15VDC, so the FET's are not being overdriven or under driven.

The dead-time is controlled by the driver IC and is fixed internally at 1.0μs. In addition, I have included four 56ohm gate resistors (to increase the dead-time? and prevent shoot-through currents), although I do not understand how to calculate this resistance or how it relates to the gate mesh resistance Rg,i. I also do not know how to derive the values for the capacitors between VS1 and VB1, VS2 and VB2 for this IC.

Each FET body-diode is isolated with a Schottky Barrier diode, connected in series with the drain lead, and external fast recovery diodes are connected across the FET and the Schottky diode to provide a path for the free-wheel current.

All semiconductors are heatsinked, I have a heavy duty 50k ohm resistor on the output of the voltage multiplier ladder, and I ramp up the power slowly through a 10Amp variac.

There are four 220nF caps paralleled, all in series with the primary winding of the output transformer, in order to eliminate the presence of any DC current in the primary winding; the output transformer is 250V:14kV, designed to run at around 40kHz and has a ferrite core.

From the recent scope measurements taken on FET gates, it appears that the lower FETS, LO2 and LO1 have reasonably square waveforms, however, the waveforms on the gates of H02 and H01 are just little spikes. These measurements were made without the transformer connected. I will repeat them again, transfomer connected and report back (with pics of the waveforms).

Doug suggested that the FET’s I’m using (SPW47N60C3 [which are 47A, 650V]) are too large for this IC to drive directly. Could anyone suggest a more robust driver IC?
Or possibly I could swap out the FET’s? I have some IXFH52N30P, which are 52A, 300V, although these are perhaps still too large?

So, with respect to point 1, turning on the FET’s, I understand that Cgd and Cgs need to be overcome by the gate drive current before the FET will turn on. On the datasheet these values are given (at 250V) as Crss = 70pF = Cgd, and Cgs = Ciss – Crss, where Ciss = 1600pF, therefore Cgs = 1530pF. The driver IC has an output source current of 180mA...
Attachments
circuit layout.jpg
copper-side circuit layout
h-bridge and driver.jpg
H-bridge circuit and driver IC
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Re: Burning FET's and driver troubles

Postby johnf » Wed Nov 17, 2010 12:53 pm

Johnathon
Not surprising you are having troubles. The high side bootstrap capacitors VB1,VB2are way too low in value.
At present 1n try 4u7 to 15uf they should only need to be 25 volt rated low esr types a must ( I usually use multiple 4u7chip 1206 ceramic).
The 1n caps will not suppy enough gate charge in fact the fets probably have more gate capacitance than the bootstrap gate supply ones.
Net effect of this is the fet will not be hard switched a sure method of letting smoke escape.
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Re: Burning FET's and driver troubles

Postby Doug Coulter » Wed Nov 17, 2010 2:20 pm

Nice post! Let's get to work on this.

I see JohnF slipped in while I was writing this and he's saying use much larger bootstrap caps. I guess we don't disagree, actually, but what I'm saying is .1u gets it if the fets aren't so huge (verified this with scope), so we are really both saying "match to the fets you're driving". He's raising the caps, I'm saying use smaller fets -- same idea, actually, but tempered with the fact that even with big caps, the chip can only do so much output current, and too big caps into too big a load just bakes the chip instead, or maybe gives you a too slow initial charge up. They do need to be high quality, low ESR caps no matter what.

You are going to need to be able to apply a scope to tune some of this stuff, so the first thing you need to do for a direct-rails supply is to have an isolation transformer so you can temporarily ground the negative rail of the big input DC supply and see gate drives and bottom fet drain waveforms -- in general, you're going to have to assume that the high side waves are the same, as trying to ground the scope to a bridge output point is futile most times due to emi issues. Without that, you're going to be constantly in the dark about what is going on.
I have been known to float the scope off ground, but not only is that dangerous as heck, there are always some parasitic couplings that find their way into the waveforms you see so it's not telling the truth anymore anyway. You can ditch the iso transformer once it all works of course. Good thing to have around for things running right off the mains when it's time to fix or tune them though.

Yes, I think your fets are probably too big for this particular chip to drive, or on the edge. Adding resistance in the gates slows down those waveforms and decreases dead time, as it slows down the turnoff seemingly more than the turn on (but that depends on the drain waveform). It's a tradeoff, because of the miller capacity (usually expressed as a charge number rather than a capacity, since the effect depends on drain volts/second and capacity, which obviously varies with drain voltage supply -- and other things, like what the load is doing just then).

What happens if the R's are too big is you start to see a glitch on the gate drive at the gate, right when the drain volts switch, which can take an off-going fet back on, or an on-turning fet back off for a little while. This is VERY bad for the fets, and is likely your main problem. From my experience with high current fets (lower volts, though) the resistors you show are much too large, and you'll have that problem with them. For reference, the fets I use are irfp 450's for high voltages, irfp 264 for somewhat lower voltages, and irfp048 for real low voltages. The middle one works best here, but then I'm running off 120v mains and not using voltage doubling on the mains supply.

I am in general shooting for under 1 kw net supply output, as a fusor really can't handle more than about half that without some serious liquid cooling of the tank anyway, and with 400-500w input I'm getting into the multiple millions neutrons/second, about my lab safety limit these days -- and that's at a "mere" 50kv HV input, it's going up in output and Q as I go higher in volts and lower in current and gas pressure with no slowing down or peak in sight yet. Which is why my nifty Spellman 50kv supply is going to be used for something else and a new higher voltage supply is getting built. The 2.5kw Spellman is way way overkill (deliberate on my part, so I could be really sure), you just can't use that much power. Running up the gas pressure to get the current up to what it can do doesn't make any more fusion than you get at 10 ma or so. In fact, you get less due to more useless collisions with stray neutrals and so forth, rather than head on ones.

I am right now building almost this exact same supply as you, Jon! It will be 120kv max, probably less in real life under load -- this is a good thing, we can share what we find out and run into pretty well. This won't be my first, by a long way, but it will be the highest voltage and largest magnetics I've done -- the transformer is most of a cubic foot. Initial results with just one stack stage (but large loads) are looking really good with this circuit. I am taking a little extra time due to the high voltage it's going to make to build a nice large box with fans and shielding and all that so I won't get killed by the kilowatt, but early bench tests are looking real good. I've run it to near full power and even in arcing conditions, no problems. Nice!

I use resistors in the ~20 ohm range with the '264's FWIW. Sometimes zero R if I'm not having oscillation problems (but this makes the chip get hot), this is PCB layout-dependent as heck, which is one reason they don't give an easy cookbook equation for it. For lower current fets (eg lower capacities and charges) you can go up a bit, for larger ones, go down in R. At some point, the chip just won't switch them fast enough, or that gate glitch will re-appear, and at that point, we have to go to some different fet driver plan. This chip is for KW and under kinds of things, not multiple KW, in my experience.

However, there are some really robust fet/igbt drivers out there (I can suggest a few) that will do serious amps peaks, but none that float -- at that point you have to go to something like a gate transformer drive circuit with a few passives up on the fet side to control rise and fall times, and some other way to adjust dead time. We can discuss that if it becomes necessary, but I think it might not be here. At least not yet. I don't know of any fat-driver chips that have the nice floating drive for top-half fets, you have to manage that outside the chips in that case.

The bootstrap caps can all be .1uf. Beware of some low volt ceramics that stop acting like true capacitors when used over their voltage ratings (Joe Sousa uses those as variable impedances by changing the DC bias across them -- even for audio power amp kinds of things, or in place of a variac for AC control!). But do get good quality .1uf ceramics at 25v or so ratings for those. This chip draws serious current spikes, so use good bypassing with a decent sized electrolytic (maybe even solid tantalum) with a smaller ceramic across it, right at the chip, it will drive the fets better that way too. Beware inductive coupling from the large fet currents into the oscillator/timing parts as well -- that one cost me a few fets when the oscillator went nuts due to that. A PCB layout change was required to really kill that problem -- I was accidentally making a transformer between the high current traces and the low level stuff that messed things up. It wasn't capacitive coupling! It was magnetic! Ow! That one took some head scratching to find and fix.

Most of this stuff you can't just brute force to solve burnup problems. Going to bigger fets means slower switching, during which time losses are high if everything else isn't perfect -- and in real life, it's never perfect. So going to huge output devices just moves problems to elsewhere without solving them. Since the fets are where the rubber meets the road (and the power source is very powerful, and the load can act like a short circuit), they are the thing that goes out, often taking the driver with them. I have actually taken out more drivers than fets when a high current glitch fed back into the driver via the capacities of the fet, so getting the fets sized right is more important than you might think at first.

One thing you need to discover is the real parameters of your load, both with and without a bleeder on the HV stack. You'll want the data with the stack connected, as it's parasitic C load will lower the resonant frequency of the secondary (usually), and in real life it will be there, so that's the numbers you need to know -- you'll be tuning the oscillator to near that frequency, probably a little below that to see an inductive load. I have good luck tuning there, or 1/3 that frequency so the 3rd harmonic of the sq wave drive doesn't see a capacitive short circuit, but often as not, the transformer resonance will be too low for that to be practical -- when I did that I was using a very high resonance transformer without a lot of secondary turns.

There are dodges and tricks to help that, but you really can't force it that much without just creating a lot of loss someplace else -- this is a finesse thing, not a brute force thing (even though the eventual output is brutish indeed!). I often find out that a small bleeder load (a few watts tops) tames down weird ringing effects at the secondary that are due to stray L's and C's in it. If you could draw the true equivalent circuit of one of these HV transformers, you'd see a lot more L's and C's and R's in it than the simple thing most people have in mind when they think "transformer" -- and they all matter in this work.

I find, for what it's worth, that a few watts (not a lot, but some) load on the stack helps get a better picture of things, and that actually low loads can be harder on drivers than big ones -- you are driving the transformer resonant circuit stored energy and it's worse when it's all in the transformer rather than the load damping some of that stuff out. To see the secondary waveform, I just place the probe near it -- an inch or so. This keeps the scope and prove alive (most won't take that kind of thing direct) and though it's a little differentiated signal, it's enough to see what's going on. Pretty much all the resonance issues are in the secondary winding -- it has the highest L and C both.

I almost always tune for least loss power at no load here, and that seems to be working out very well -- haven't fried a power supply in awhile now. Without a bleeder on the stack, you should be able to get into the low milliamps draw from the fet main supply rails. If you can't -- find out why and fix it! Only then go for real power output. If you have something like a shorted turn in the transformer, well, that's very sad, but you'll have to fix it before proceeding. You should see the no load current draw go up more or less linear with the fet rail volts. If it goes up faster than linear, you're magnetics are going into saturation...not good and it won't be very reliable doing that. Most transformers will look like a pretty high Q resonant circuit, unless there's a lot of leakage L or R someplace (a little of that is GOOD, too much is BAD).

With medium sized fets, you can look at how well the drain of a lower fet in the bridge gets to ground and see the current being drawn vs time on a scope nicely, using the fet on-resistance as a current sensing resistor -- no good for absolute numbers, but good to see the current waveform shape. I find this really helpful in tuning, along with watching the gate waveform on the same fet (dual trace scope). As I usually tune for a slightly inductive load, what I see when things are right is that the instant the fet I'm watching is turned off, the drain flies all the way to the other rail (caught by the other fets freewheeling diode), so when the other fet turns on after the dead time, it's already got zero (or even 1 diode drop negative) volts across it -- that's a nicely low-loss situation. This will change some with output loading of course, but it's what you are shooting for with fets (with IGBTS the problems are all different, and this tuning ruins them quick due to getting outside their safe operating area during the turnoff, which they aren't so good at, being basically transistors with storage times). I've not yet had to use extra diodes here, when things are right, the body diode of a modern fet seems to do well enough.

I'm not going to say it's a bad idea, though, just that you may not actually need it. Here, my fets don't even get warm on a 1" sq heatsink each at no load...at real high loads they do need heatsinks due to voltage drops during on time, but not at idle. If you can't get to there, it'll never fly in real life. Not as fun as full power testing, but it's the way to get it there.

At the drain, you'll see either a ringing during the on time (a small signal, the fet is on and a decently low resistance, but you can still see stuff if you crank the scope gain up). If you see a current ramp up during the on time, that's nice if it's linear. If it's going parabolic ally up at the end of the on time -- you are saturating your transformer and trying to cheat mother nature -- we all know how that turns out. Getting the circuit to match the magnetics is key, however you get there. It's usually easier to do the circuit, because changing the magnetics means a lot more work in general. Turning a fet off while the current is high means a lot of switching loss during the turnoff time as well.

In the event your magnetics have a too-low resonant frequency for you (because maybe the AC side caps in the stack are small and you're concerned about voltage losses there) there is a popular dodge for that -- wire a high quality (large in size but low in inductance) inductor across the primary to raise the resonance you see. You can only take this so far, however. You're not going to easily get an octave out of that trick (which would require cutting the inductance of the primary by factor 4), and losses due to the secondary resistance are going to go up, as well as losses in the primary and the inductor you add there -- the secondary winding still has its resonance in the same place, after all. It's kind of trying to cheat, but for small changes it's workable -- but not octaves. Once you have done this, you can expect to see more quiescent current at no load due to winding losses, of course, and at some point there will be temperature rise in the magnetics that may be too much for you. Most of these cores, however, are at their best when on the warm side -- the magnetic properties are somewhat temperature sensitive. so running at 50-80 C isn't all that bad for most of them, and indeed might be better than "cold" -- depends on the ferrite used. Ideally, you'd want to be in the range of 25-50khz for a large supply, I've gone up to 70khz for smaller ones when the transformer allowed that. (which is about the limit of this chip anyway) But you have to deal with what transformer you have (or are willing to make).

For what it's worth, I've run mine with and without the series C to the transformer primary without any noticeable changes, this particular circuit, and good fets just doesn't seem to have an imbalance issue at all -- nice. However, a slick trick to do is to make a series resonant LC at your tuning frequency, instead of just a C there (which means you can use a smaller C too, but it has to be a good one with low ESR). The thing that helps with is providing a higher impedance, inductive, to the high harmonics of the fast rising square wave, which can cut switching losses in the fets way down -- and also protect them if for some reason you get way off tune because off the resonance of the series LC, the load impedance goes up so the thing can't draw as much current through the fets. I have not had to do this here, as I wind my own transformers mostly, and get a similar effect by controlling the leakage inductance between primary and secondary, for example, winding at least part of the primary on the leg of the core on the other side from the secondary. Learned that trick analyzing some Glassman output magnetics, and it really works nicely if done right. This turns out simpler (less parts) and more efficient than the multiple L's and C's in the output circuit. The Wallis transformer I'm currently messing with doesn't do this, but has plenty of leakage L and a fairly complex impedance vs frequency plot for one of these, but I've not taken it far enough apart to discover why yet. At any rate, the fact that it has odd frequencies where it acts like an open circuit is actually a good thing as it cuts power losses in the driver on the fast edges.

But in general, what you are shooting for here is to get the fets to switch just as the magnetics resonance is trying to do that anyway -- then the fets just hold the state after the switch. You don't want to go so slow that the magnetics are trying to really switch HARD at that instant, because then the fet that's turning off is switching at high current, which is lossy, and makes the drain waveform have so much dv/dt that you get glitching back on the gate, which turns into a downhill spiral real quick and lets out the magic blue smoke quite effectively.

I have also (for some transformers, but not all) actually gotten a situation where when the bottom fet turns off the drain just goes to the middle for the deadtime, and then the top fet turns on and drags it to the top rail, and that worked out well too. But it's rare, and quite difficult to stay tuned on to.

What you very much don't want to see is backing and forthing during the deadtime -- that's pure poison for the fets. It can be caused by too high an R in the fet gate as well as by plain old mis tuning. That glitch on the gate drive can keep a fet in its linear range, neither on nor off, dissipating serious power -- and they go boom. I find, by the way, that I can do most of this tuning with something like 24v on the fet rails, then just watch carefully as I crank the rails up to the "real" operating voltage range, then back down for any tuning needed to make that area happy. That makes it easy to do, and around here high current 24v isolated supplies are easier to put hands on than big fat isolation transformers at mains voltages. This keeps me from getting killed trying to adjust things while they are at hazardous voltages as well.

I will sometimes see some sinusoidal ringing on the low fet drain during on time due to some higher order resonance in the magnetics. I've not had it make trouble, but then I do tune for the nice waveform on turn-off and that takes this into account most times.

I'll have to put CliffS name in here, in case he's watching. His word is THE word on this stuff, and if we run into any real troubles here, we can hope he'll bail us out a bit. That book on Switching Power Supply Design by Abraham I Pressman is hard to beat as well -- nothing in it is untrue in my experience with switchers, and a little was even new to me. That doesn't happen real often, so I'm real grateful for JohnF telling us about it.

Screenshot-1.png
PCB layout in trax/dos/linux software


Here's the layout I wound up with after a couple of tries. Fets across the top so they all go on the same heatsink and the wiring is "tight". I stiffened up the high current tracks with wire, and use an 82 uF bypass electrolytic across the main rails. One way of knowing if you're tuning right is that thing gets HOT if you aren't. Any farther away is too far away for that cap to be.
Note the ground rail at the bottom isn't wired to the main rail minus -- that's on purpose so I could insert current sensing there. I had to add a wire from the cap (on the right) to the + rail for the fets (center top) because of the limitations of a single sided PCB (made here). I have a trimpot for oscillator tuning, and a series R in that so the pot isn't too wide a tuning range and hard to adjust. For what it's worth, I found using a super-high quality silver mica timing cap was a bad thing, and a crummier ceramic actually works out better. Go figure. I used a 3 terminal 15 volt regulator for the chip to keep the chip cooler. Don't know how important that would be in yours, but it helps here.
Posting as just me, not as the forum owner. Everything I say is "in my opinion" and YMMV -- which should go for everyone without saying.
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Re: Burning FET's and driver troubles

Postby chrismb » Wed Nov 17, 2010 2:38 pm

I was going to ask about the relevance of low ESR caps. I run my own charge pump circuits on P-N bridges so it is a circuit of 'discretes' rather than what's in a chip.

I'm assuming this thread is talking about just the bootstrap capacitor, and that it doesn't serve some other additional function in a chip-based circuit?...

I stuck in 100uF 25V 'regular' electrolytics, because that was the first bag of caps I pulled out of my box! It is only there as a 'battery' to bounce up and down on top of the switching voltage to power the gate, so it can be as big as you like as its voltage should be as steady as you like, not that it is varying. It recharges off of the high voltage each time it gets pulled lower than it (as it looses just a little charge each cycle, powering the capacitance on the gate), and because I run MHz so my bootstrap diode of choice are BAT85s. I don't know if the diodes in these chips are quicker that BAT85s, but that's well quick enough at a few MHz switching!
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Re: Burning FET's and driver troubles

Postby Doug Coulter » Wed Nov 17, 2010 2:52 pm

Actually, yes, low ESR is important to this chip -- there are some decently large currents drawn from it at switching points. It doesn't use diodes, but fets to do the charging(!), and there are limits on those peak currents, so I don't advise using real big caps there, but it may work -- I just haven't tried it because there was no apparent need to. This chip won't do amps of peak drive current anyway, so big caps, were they needed, would just fry it, I think -- this chip is meant for offline use in the single kw and below range, not for driving huge charges on huge devices. With the .1 uf (but good ones) I'm not seeing any issues with drive to the top fets I can notice in real life. In other words, it's peak current drive is well under an amp, which is enough for medium size fets at these speeds and feeds. At MHZ, you'd use one of those fancy 10 amp peak driver chips in a TO-220 package or similar. Here we just can't (and don't need to) go that fast, and too fast is hard on things and makes too much EMI anyway. Too quick a dv/dt on the drain makes too much current required back in the gate drive circuit, and doesn't really save you much if anything on fet heating anyway.

Jon -- did you try monitoring the temperature on the fets? Do they get hot, or blow while cold from some spike? That's worthwhile to know about. They should pretty much be staying cold at low or no load. Also I don't see filter caps on your main rails -- which could be good or bad, as JohnF pointed out on the other thread about the one I'm building -- a current-fed version (bascially another switcher driving the rails here in current mode) may be the way to go, eventually. Since this chip has deadtime (entirely too much from my POV) you'd still need a little filtering to keep the rail volts from jumping up high during that time. But having 100hz full-value ripple here can't be good for things the way you are showing this -- with the little caps in the stack it will show up in the output for starters. For now, I'm using a rather large set of filter caps, but plan to try the current-fed topology real soon, as it gives better control and a way to do constant current limiting on the output, which I'm finding is real nice to have on a fusor.
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Re: Burning FET's and driver troubles

Postby JonathanH13 » Fri Nov 19, 2010 7:07 am

Thanks for your very thorough replies and insight – it all makes a lot more sense now.
OK, some quick feedback on progress so far:
I replaced the caps with some 4u7 tantalums that I have to hand - they have low esr, but not ultra low (I also ordered a range of ultra low tantalums yesterday). This made a huge difference (I immediately found an interesting triangular wave on the output. I then replaced all the 56ohm resistors with 15 ohms. This made another huge difference - the triangular shaped wave pulled itself up into a pretty decent square wave. Unfortunately that is where the improvements ended.
I do indeed have several glitches (see the third pic): The most serious looking one is a negative going spike just before the turn-on slope at the gate drive. The next glitch is just after the start of the turn-on slope, and there are another two on the turn-off slope. I have tried several different values (15, 12 and 6 ohm) for the gate resistor and several different cap values (4u7, 9u4 and 14uF) for the bootstrap capacitors. None of these values or combinations thereof makes any difference to the wave shape, nor do they improve the glitches. They only thing that does improve things slightly is turning down the power supply from 15 to 12 volts...
I have a battery powered portable Fluke 199C scope, which is floating, by definition. So I think that I can measure anything that I could measure using an isolation transformer/scope combination? I am measuring this gate signal with the ground lead of the scope probe attached to the rectified AC- line, and the probe to HO2. If I place the probe’s ground lead to VS2 (the bridge output point) and the probe to HO2, then all the glitches disappear! What does this mean? The glitch is on the low side of the bridge?

Another thing that I noticed is that the high side gate signal is only 10 volts, whereas the low side is the full 15v. This is not right, surely?

>monitoring the temperature on the fets.
I do try to keep an eye on this - they always seem to be cool, although HO1, (which seems to blow preferentially) did have a suspicious yellow discoloration on the copper (the heatsink is copper), as if it had momentarily become very hot. I have never caught it 'in the act' though.
> I don't see filter caps on your main rails.
I do have two 470nF polyprops across the rails (although I must confess that I’m not sure if these values are appropriate).

I have the book that you recommend, and am making my way through it. Wow! What a gem - lots to learn!
Attachments
LO2&ac- 5vd.JPG
LO2-Ground (5 volts per division)
HO2&VS2 2vd.JPG
HO2-VS2 (2 volts per division)
13ohms 2vd.JPG
HO2-Ground (2 volts per division)
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Re: Burning FET's and driver troubles

Postby Doug Coulter » Fri Nov 19, 2010 9:46 am

What I see instantly is that the chip can't get a good fast rise or fall time into that gate load. That means slow turnon and off of the fets, and they will die when current is being drawn during those times. 10v drive should be OK, actually, but you have to get there quick. That's showing that either the chip can't charge those large caps fully, or they are not so good some other way.
Could be the stuff in the chip simply wimps out at the currents required -- it should be within a volt of so of the chip power supply voltage. With most fets, the actual threshold is about 4v or so, and how fast you can move through that is the key. At 10v or so, you're getting it as turned on at high load currents as it's going to get if you look at the fet spec sheets. I can't quite make out your horizontal speed/division, but assuming you are running some sane frequency, those rises and falls are just too slow. The fets are spending much too much time in a linear region with both voltage and current across them with that drive waveform. Your rise and fall times shouldn't be 10 or 20% of the total time as I see here -- that will get things very hot under real loads, and risks getting out of the safe operating area of the fets. (Thank heavens you're not running with igbts, or they'd die with this even with no load at all!)

It might be counterintuitive, but with less fet that gets fully switched quicker, you don't have that loss anymore, and then only have the loss during on time due to the finite on resistance, which is still going to be pretty low even with a smaller fet. Though heat is heat, and fets have a pretty square SOA, it's still a lot easier on them to not be dithering around during the switch interval, and a smaller fet should actually run cooler and be more robust here (or a much fatter drive -- amperes instead of the milliamps this chip makes).

You're going to need more drive, or less fet. I'd go with the latter myself (because it makes the rest simpler and all of it cheaper), but that's a call you have to make. I don't know your power output target, but this chip is for KW and down kinds of things. If you're really going to run full rectified 240v AC on the rails, I'd go with the industry standard IRF 450 600v fet there. That's more or less what this chip was meant to mate with, and there's a good reason that it's the one you find inside any FET based commercial HV power supply when you peek inside - regardless of the brand. They'll do a KW pretty easily when the other things are right. After all, with 240 *1.414 = 339vdc and 10 amps (the fets are rated for more on a heatsink) you've got over 3kw possible there -- and you can't use it, really. Your fusor tank will melt a good bit before that -- not to mention the grid. It's all going to come back as heat and X rays.

I'd have more to say if I could see one of the bridge outputs into the load -- Ho2 to gnd includes that but adds the gate drive, so it's not as informative. The output where any backing and forthing, or just slow rises/falls makes the big difference. It would also show me enough to perhaps suggest if you're tuned way off in frequency from what the magnetics desire. VS2 to negative main rail, for example.

Usually, you'd use at least 1000 uf/amp of load on a main power supply. Else all this is going to go up and down with the mains frequency when loaded, with some bizarre results.
I don't see evidence of mains ripple on these waveforms, which makes me a little curious. The poly caps there will help with the fast stuff, but you need bulk filtering to coast through the times when the mains AC is making zero crossings. Luckily with this chip, either the chip or the fets power can go to zero and come back at any time without doing damage, but you won't want severe ripple on the supply output, and the caps in the stack aren't going to cover that well at all. They are only meant to be good enough for much higher frequencies where their impedance is low. Further, having them run down and then have to recharge fully each mains half cycle is going to put a lot of unnecessary stress on the stack diodes -- not good.

FWIW, I run a snubber between the two output points of about 1000pf and 100ohms (10w resistor) and it helps a bit. Basically, you increase the cap until you don't like how hot the resistor is getting -- you want to burn a few watts there in what looks like a resistive load at the real high frequency components of the edge.

What I've found is even with battery or otherwise floated scopes is, nope, you can't have the scope ground making fast ups and downs without the capacitive coupling from the scope internals to the rest of the planet injecting some of that into the trace. You might be lucky, but it'd be luck, unless the innards are shielded to a level that would make the spooks secure comms guys jealous. (TEMPEST for those who know what that means). Try it with the ground on a hot fast sq wave such as this should produce, with the probe simply shorted and see if you don't see some signal anyway -- enough to confuse what you're attempting to observe. Even pretty high quality/dollar scopes suffer from this one.

One reason we want to be thorough here is so we can direct the next guy to this thread, and easily answer most of his questions thereby. Not everyone is going to buy and comprehend that book and have no problems after all, so this is kind of our version as it applies to this field of use. Far too many assume they can brute force their way out of a switching power supply problem, but it just ain't so, and this is going to be a nice demo of that truth. Finesse rules here, not force, and too-large components make more problems than they solve, more often than not.
Posting as just me, not as the forum owner. Everything I say is "in my opinion" and YMMV -- which should go for everyone without saying.
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Re: Burning FET's and driver troubles

Postby chrismb » Fri Nov 19, 2010 9:49 am

Let me know if I am missing or misunderstanding something here, but I have always assumed the rise/fall time would, in general approximations, be simply a function of the total gate charge and the driver current, as read off the data sheet. This is why I use a 9A driver with FETs of ~10nC, giving a risetime of ~ns (viewtopic.php?f=8&t=169). If I read the same numbers off of these data sheets, the IRS2453 has a driver current of 0.2A and the gate charge for the SPW47N60C3 are 300nC, giving a rise time of ~2us, as per your trace.

During the slow switch-on then you may get resistive conductance through the FET.

So if the above holds true, then if you want harder switching to achieve lower FET losses then you have to switch with higher currents or smaller FETs.

Another thing that I noticed is that the high side gate signal is only 10 volts, whereas the low side is the full 15v. This is not right, surely?
The data sheet says the push-to-pull current is lower, so maybe it is something to do with the gate not fully charging, again a driver current versus gate capacitance issue.

How long are the runs to the gates? At these speeds inductive behaviour is probably not so important, but always worth keeping driver-gate runs as short as poss.

I also don't bother running gate resistors. In my, albeit limited, experience the drivers seem to be happy with that - but, again, short runs to a low capacitance gate are probably the reason why 'no-resistors' works out OK for me.
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Re: Burning FET's and driver troubles

Postby Doug Coulter » Fri Nov 19, 2010 10:13 am

Chris, when I try no resistors, we get troubles with the chip overheating -- theoretically infinite current with trying to drive a capacitor with a fast edge. Better to let the R's take that heat, and let the gate catch up after the chip is fully switched to a rail.

Further, in the event of an output arc that makes (reflects) fast edges on the fet outputs, that charge tries to blow back through the driver chip and those R's keep it alive during that -- current limiting.

Remember, you're not driving a big tuned circuit with a bunch of stored energy in it, and in the CW stack after it, like he is. These chips are rated in the sub-amp drive range, as you noted. If you push too large a spike back into them, you might even take the chip power rails above 15v and fry it that way. Finesse!

This circuit is "deceptively simple" but that doesn't mean "actually simple" at all.

With the fets he's using, it's like trying to pull a freight train with a tricyle -- it's not going to be pretty. We could maybe invent a stouter driver, but that's a fair amount of work compared to just replacing with (cheaper anyway) smaller fets that are easier to drive. And still plenty big enough to do the job.

Your assumption of it being current vs gate total charge is correct -- remembering that the actual gate charge is a function of the C's in the fet AND the drain voltage both, being "millered" into that gate, which multiplies the gate-drain capacity.

Seems I forgot to post this earlier, it's not very good but does show some of the effects of tuning. I was using a too-stiff snubber at the time, which was most of the actual current drain.
Fixed that now, and the waves look a lot better. Top trace is gate drive on a low side fet, bottom trace is the output waveform with the transformer and one stack disk load.


The glitch on the output during the switch time at "minimum net current drain" is happening during the fet dead time, and is no problem in this particular case. When the other fet pair turns on, it yanks things to the other rails fine and fast. You can't see it well here, as my vid cam won't get close enough in focus to show it very well -- got to work on that some. I now have some software that will capture scope screens into the PC at a couple of hz capture rate, so maybe I'll try with that.
Posting as just me, not as the forum owner. Everything I say is "in my opinion" and YMMV -- which should go for everyone without saying.
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Re: Burning FET's and driver troubles

Postby Doug Coulter » Fri Nov 19, 2010 11:23 am

For reference, this is what I'm testing with now, a different transformer (homebrew) and what appears to be a stage from a Spellman supply (acquired surplus) that someone foolishly dug out of the potting material -- it won't go to it's rated volts in air, but is plenty hefty -- I can easily push a KW through this setup. I will note that just moving the primary from under the secondary to the other side of the core made some very dramatic differences in how hard this was to drive while staying cool --a little leakage inductance goes a long way sometimes.
BridgeSetup.jpg
Bridge setup on my tinker bench.


The perf board on the lower left is the housekeeping and chip power supply, a little fancier than needed, but it's going to run fans and a microprocessor as well in the final rig -- it makes two floating outputs. The main H bridge is at the top, and hopefully the rest is obvious. I've been using this to test a bunch of those big yellow HV caps we also got surplus, and to test the driver in arc situations, which it now passes with flying colors -- I like that. The big Wallis transformer is actually a lot easier to drive due to a lot of leakage L in various places in it, gaps in the huge core, and the big pie wound secondaries that have some leakage L and R. This little transformer borders on being "too tight" and is when the primary and secondary are on the same core leg.

At this point I'm driving it off a bench supply with current limiting so I don't have to replace fets (almost) no matter what happens. With the full rails power, it's another story, so it's easier to get it right this way, then do the more risky thing. The fets in use here are irfp-264's which are a little on the large side for this chip but it makes it -- just.
irfp264.pdf
irfp 264 data
(147.04 KiB) Downloaded 332 times

I'm using these because I get to full output on the Wallis transformer at a mere 125v on the H bridge rails. For Jon, I'd reccomend using the '450 instead, if he needs more volts to get there.
Here's the sheet for it.
IRF450.pdf
irf 450
(144.64 KiB) Downloaded 345 times


Edit -- oops, wrong data sheet, you want the IRFP-450, which is just about the same thing in the other package.

That one's more than plenty for a fusor, and is what is in both Spellman and Glassman supplies to pretty high net power outputs. Above that they both go to IGBT's (or more fets and transformers in the case of Glassman) which have a slew of problems that are different, mainly slow turnoff no matter the gate drive, and a not-square safe operating area that means you can fry a 200 amp one with 20 amps during turnoff...so other things have to be a lot more "right on" to make them live, despite numbers that look better until you examine them more closely.
Posting as just me, not as the forum owner. Everything I say is "in my opinion" and YMMV -- which should go for everyone without saying.
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